Apparatus and method for vectorization with speculation support

ABSTRACT

An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

FIELD OF THE INVENTION

Embodiments of the invention relate generally to the field of computersystems. More particularly, the embodiments of the invention relate toan apparatus and method for speculation support to enable vectorization.

BACKGROUND General Background

An instruction set, or instruction set architecture (ISA), is the partof the computer architecture related to programming, and may include thenative data types, instructions, register architecture, addressingmodes, memory architecture, interrupt and exception handling, andexternal input and output (I/O). The term instruction generally refersherein to macro-instructions—that is instructions that are provided tothe processor (or instruction converter that translates (e.g., usingstatic binary translation, dynamic binary translation including dynamiccompilation), morphs, emulates, or otherwise converts an instruction toone or more other instructions to be processed by the processor) forexecution—as opposed to micro-instructions or micro-operations(micro-ops)—that is the result of a processor's decoder decodingmacro-instructions.

The ISA is distinguished from the microarchitecture, which is theinternal design of the processor implementing the instruction set.Processors with different microarchitectures can share a commoninstruction set. For example, Intel® Pentium 4 processors, Intel® Core™processors, and processors from Advanced Micro Devices, Inc. ofSunnyvale Calif. implement nearly identical versions of the x86instruction set (with some extensions that have been added with newerversions), but have different internal designs. For example, the sameregister architecture of the ISA may be implemented in different ways indifferent microarchitectures using well-known techniques, includingdedicated physical registers, one or more dynamically allocated physicalregisters using a register renaming mechanism (e.g., the use of aRegister Alias Table (RAT), a Reorder Buffer (ROB), and a retirementregister file; the use of multiple maps and a pool of registers), etc.Unless otherwise specified, the phrases register architecture, registerfile, and register are used herein to refer to that which is visible tothe software/programmer and the manner in which instructions specifyregisters. Where a specificity is desired, the adjective logical,architectural, or software visible will be used to indicateregisters/files in the register architecture, while different adjectiveswill be used to designation registers in a given microarchitecture(e.g., physical register, reorder buffer, retirement register, registerpool).

An instruction set includes one or more instruction formats. A giveninstruction format defines various fields (number of bits, location ofbits) to specify, among other things, the operation to be performed(opcode) and the operand(s) on which that operation is to be performed.Some instruction formats are further broken down though the definitionof instruction templates (or subformats). For example, the instructiontemplates of a given instruction format may be defined to have differentsubsets of the instruction format's fields (the included fields aretypically in the same order, but at least some have different bitpositions because there are less fields included) and/or defined to havea given field interpreted differently. Thus, each instruction of an ISAis expressed using a given instruction format (and, if defined, in agiven one of the instruction templates of that instruction format) andincludes fields for specifying the operation and the operands. Forexample, an exemplary ADD instruction has a specific opcode and aninstruction format that includes an opcode field to specify that opcodeand operand fields to select operands (source1/destination and source2);and an occurrence of this ADD instruction in an instruction stream willhave specific contents in the operand fields that select specificoperands.

Scientific, financial, auto-vectorized general purpose, RMS(recognition, mining, and synthesis), and visual and multimediaapplications (e.g., 2D/3D graphics, image processing, videocompression/decompression, voice recognition algorithms and audiomanipulation) often require the same operation to be performed on alarge number of data items (referred to as “data parallelism”). SingleInstruction Multiple Data (SIMD) refers to a type of instruction thatcauses a processor to perform an operation on multiple data items. SIMDtechnology is especially suited to processors that can logically dividethe bits in a register into a number of fixed-sized data elements, eachof which represents a separate value. For example, the bits in a 256-bitregister may be specified as a source operand to be operated on as fourseparate 64-bit packed data elements (quad-word (Q) size data elements),eight separate 32-bit packed data elements (double word (D) size dataelements), sixteen separate 16-bit packed data elements (word (W) sizedata elements), or thirty-two separate 8-bit data elements (byte (B)size data elements). This type of data is referred to as packed datatype or vector data type, and operands of this data type are referred toas packed data operands or vector operands. In other words, a packeddata item or vector refers to a sequence of packed data elements, and apacked data operand or a vector operand is a source or destinationoperand of a SIMD instruction (also known as a packed data instructionor a vector instruction).

By way of example, one type of SIMD instruction specifies a singlevector operation to be performed on two source vector operands in avertical fashion to generate a destination vector operand (also referredto as a result vector operand) of the same size, with the same number ofdata elements, and in the same data element order. The data elements inthe source vector operands are referred to as source data elements,while the data elements in the destination vector operand are referredto a destination or result data elements. These source vector operandsare of the same size and contain data elements of the same width, andthus they contain the same number of data elements. The source dataelements in the same bit positions in the two source vector operandsform pairs of data elements (also referred to as corresponding dataelements; that is, the data element in data element position 0 of eachsource operand correspond, the data element in data element position 1of each source operand correspond, and so on). The operation specifiedby that SIMD instruction is performed separately on each of these pairsof source data elements to generate a matching number of result dataelements, and thus each pair of source data elements has a correspondingresult data element. Since the operation is vertical and since theresult vector operand is the same size, has the same number of dataelements, and the result data elements are stored in the same dataelement order as the source vector operands, the result data elementsare in the same bit positions of the result vector operand as theircorresponding pair of source data elements in the source vectoroperands. In addition to this exemplary type of SIMD instruction, thereare a variety of other types of SIMD instructions (e.g., that has onlyone or has more than two source vector operands, that operate in ahorizontal fashion, that generates a result vector operand that is of adifferent size, that has a different size data elements, and/or that hasa different data element order). It should be understood that the termdestination vector operand (or destination operand) is defined as thedirect result of performing the operation specified by an instruction,including the storage of that destination operand at a location (be it aregister or at a memory address specified by that instruction) so thatit may be accessed as a source operand by another instruction (byspecification of that same location by the another instruction).

The SIMD technology, such as that employed by the Intel® Core™processors having an instruction set including x86, MMX™, Streaming SIMDExtensions (SSE), SSE2, SSE3, SSE4.1, and SSE4.2 instructions, hasenabled a significant improvement in application performance. Anadditional set of SIMD extensions, referred to the Advanced VectorExtensions (AVX) (AVX1 and AVX2) and using the Vector Extensions (VEX)coding scheme, has been, has been released and/or published (e.g., seeIntel® 64 and IA-32 Architectures Software Developers Manual, October2011; and see Intel® Advanced Vector Extensions Programming Reference,June 2011).

BACKGROUND RELATED TO THE EMBODIMENTS OF THE INVENTION

Certain loops cannot be vectorized due to conditional exits from theloop and/or due to the presence of conditional data dependences. If theconditional exits are not taken frequently or the data dependences don'tmaterialize frequently it is beneficial to speculatively vectorize theloop, detect when exits are taken or dependences materialize and honorthem through the use of predication or masked SIMD/vector operations.Often memory loads occur early in the dependence chain and withoutsupport for speculation dynamic dependences cannot be detected and hencethe loop cannot be vectorized.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description and accompanying drawings are used toillustrate embodiments of the invention. In the drawings:

FIG. 1A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention;

FIG. 1B is a block diagram illustrating both an exemplary embodiment ofan in-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention;

FIG. 2 is a block diagram of a single core processor and a multicoreprocessor with integrated memory controller and graphics according toembodiments of the invention;

FIG. 3 illustrates a block diagram of a system in accordance with oneembodiment of the present invention;

FIG. 4 illustrates a block diagram of a second system in accordance withan embodiment of the present invention;

FIG. 5 illustrates a block diagram of a third system in accordance withan embodiment of the present invention;

FIG. 6 illustrates a block diagram of a system on a chip (SoC) inaccordance with an embodiment of the present invention;

FIG. 7 illustrates a block diagram contrasting the use of a softwareinstruction converter to convert binary instructions in a sourceinstruction set to binary instructions in a target instruction setaccording to embodiments of the invention;

FIG. 8 illustrates a specific example of the operation of one embodimentof the invention;

FIG. 9 illustrates one embodiment of the invention for vectorizationwith speculation support;

FIG. 10 illustrates a gather finite state machine (FSM) employed in oneembodiment of the invention;

FIGS. 11A and 11B are block diagrams illustrating a generic vectorfriendly instruction format and instruction templates thereof accordingto embodiments of the invention;

FIG. 12 is a block diagram illustrating an exemplary specific vectorfriendly instruction format according to embodiments of the invention;

FIG. 13 is a block diagram of a register architecture according to oneembodiment of the invention;

FIG. 14A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network and with its local subsetof the Level 2 (L2) cache, according to embodiments of the invention;and

FIG. 14B is an expanded view of part of the processor core in FIG. 14Aaccording to embodiments of the invention.

DETAILED DESCRIPTION Exemplary Processor Architectures and Data Types

FIG. 1A is a block diagram illustrating both an exemplary in-orderpipeline and an exemplary register renaming, out-of-orderissue/execution pipeline according to embodiments of the invention. FIG.1B is a block diagram illustrating both an exemplary embodiment of anin-order architecture core and an exemplary register renaming,out-of-order issue/execution architecture core to be included in aprocessor according to embodiments of the invention. The solid linedboxes in FIGS. 1A-B illustrate the in-order pipeline and in-order core,while the optional addition of the dashed lined boxes illustrates theregister renaming, out-of-order issue/execution pipeline and core. Giventhat the in-order aspect is a subset of the out-of-order aspect, theout-of-order aspect will be described.

In FIG. 1A, a processor pipeline 100 includes a fetch stage 102, alength decode stage 104, a decode stage 106, an allocation stage 108, arenaming stage 110, a scheduling (also known as a dispatch or issue)stage 112, a register read/memory read stage 114, an execute stage 116,a write back/memory write stage 118, an exception handling stage 122,and a commit stage 124.

FIG. 1B shows processor core 190 including a front end unit 130 coupledto an execution engine unit 150, and both are coupled to a memory unit170. The core 190 may be a reduced instruction set computing (RISC)core, a complex instruction set computing (CISC) core, a very longinstruction word (VLIW) core, or a hybrid or alternative core type. Asyet another option, the core 190 may be a special-purpose core, such as,for example, a network or communication core, compression engine,coprocessor core, general purpose computing graphics processing unit(GPGPU) core, graphics core, or the like.

The front end unit 130 includes a branch prediction unit 132 coupled toan instruction cache unit 134, which is coupled to an instructiontranslation lookaside buffer (TLB) 136, which is coupled to aninstruction fetch unit 138, which is coupled to a decode unit 140. Thedecode unit 140 (or decoder) may decode instructions, and generate as anoutput one or more micro-operations, micro-code entry points,microinstructions, other instructions, or other control signals, whichare decoded from, or which otherwise reflect, or are derived from, theoriginal instructions. The decode unit 140 may be implemented usingvarious different mechanisms. Examples of suitable mechanisms include,but are not limited to, look-up tables, hardware implementations,programmable logic arrays (PLAs), microcode read only memories (ROMs),etc. In one embodiment, the core 190 includes a microcode ROM or othermedium that stores microcode for certain macroinstructions (e.g., indecode unit 140 or otherwise within the front end unit 130). The decodeunit 140 is coupled to a rename/allocator unit 152 in the executionengine unit 150.

The execution engine unit 150 includes the rename/allocator unit 152coupled to a retirement unit 154 and a set of one or more schedulerunit(s) 156. The scheduler unit(s) 156 represents any number ofdifferent schedulers, including reservations stations, centralinstruction window, etc. The scheduler unit(s) 156 is coupled to thephysical register file(s) unit(s) 158. Each of the physical registerfile(s) units 158 represents one or more physical register files,different ones of which store one or more different data types, such asscalar integer, scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point, status (e.g., aninstruction pointer that is the address of the next instruction to beexecuted), etc. In one embodiment, the physical register file(s) unit158 comprises a vector registers unit, a write mask registers unit, anda scalar registers unit. These register units may provide architecturalvector registers, vector mask registers, and general purpose registers.The physical register file(s) unit(s) 158 is overlapped by theretirement unit 154 to illustrate various ways in which registerrenaming and out-of-order execution may be implemented (e.g., using areorder buffer(s) and a retirement register file(s); using a futurefile(s), a history buffer(s), and a retirement register file(s); using aregister maps and a pool of registers; etc.). The retirement unit 154and the physical register file(s) unit(s) 158 are coupled to theexecution cluster(s) 160. The execution cluster(s) 160 includes a set ofone or more execution units 162 and a set of one or more memory accessunits 164. The execution units 162 may perform various operations (e.g.,shifts, addition, subtraction, multiplication) and on various types ofdata (e.g., scalar floating point, packed integer, packed floatingpoint, vector integer, vector floating point). While some embodimentsmay include a number of execution units dedicated to specific functionsor sets of functions, other embodiments may include only one executionunit or multiple execution units that all perform all functions. Thescheduler unit(s) 156, physical register file(s) unit(s) 158, andexecution cluster(s) 160 are shown as being possibly plural becausecertain embodiments create separate pipelines for certain types ofdata/operations (e.g., a scalar integer pipeline, a scalar floatingpoint/packed integer/packed floating point/vector integer/vectorfloating point pipeline, and/or a memory access pipeline that each havetheir own scheduler unit, physical register file(s) unit, and/orexecution cluster—and in the case of a separate memory access pipeline,certain embodiments are implemented in which only the execution clusterof this pipeline has the memory access unit(s) 164). It should also beunderstood that where separate pipelines are used, one or more of thesepipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units 164 is coupled to the memory unit 170,which includes a data TLB unit 172 coupled to a data cache unit 174coupled to a level 2 (L2) cache unit 176. In one exemplary embodiment,the memory access units 164 may include a load unit, a store addressunit, and a store data unit, each of which is coupled to the data TLBunit 172 in the memory unit 170. The instruction cache unit 134 isfurther coupled to a level 2 (L2) cache unit 176 in the memory unit 170.The L2 cache unit 176 is coupled to one or more other levels of cacheand eventually to a main memory.

By way of example, the exemplary register renaming, out-of-orderissue/execution core architecture may implement the pipeline 100 asfollows: 1) the instruction fetch 138 performs the fetch and lengthdecoding stages 102 and 104; 2) the decode unit 140 performs the decodestage 106; 3) the rename/allocator unit 152 performs the allocationstage 108 and renaming stage 110; 4) the scheduler unit(s) 156 performsthe schedule stage 112; 5) the physical register file(s) unit(s) 158 andthe memory unit 170 perform the register read/memory read stage 114; theexecution cluster 160 perform the execute stage 116; 6) the memory unit170 and the physical register file(s) unit(s) 158 perform the writeback/memory write stage 118; 7) various units may be involved in theexception handling stage 122; and 8) the retirement unit 154 and thephysical register file(s) unit(s) 158 perform the commit stage 124.

The core 190 may support one or more instructions sets (e.g., the x86instruction set (with some extensions that have been added with newerversions); the MIPS instruction set of MIPS Technologies of Sunnyvale,Calif.; the ARM instruction set (with optional additional extensionssuch as NEON) of ARM Holdings of Sunnyvale, Calif.), including theinstruction(s) described herein. In one embodiment, the core 190includes logic to support a packed data instruction set extension (e.g.,AVX1, AVX2, and/or some form of the generic vector friendly instructionformat (U=0 and/or U=1), described below), thereby allowing theoperations used by many multimedia applications to be performed usingpacked data.

It should be understood that the core may support multithreading(executing two or more parallel sets of operations or threads), and maydo so in a variety of ways including time sliced multithreading,simultaneous multithreading (where a single physical core provides alogical core for each of the threads that physical core issimultaneously multithreading), or a combination thereof (e.g., timesliced fetching and decoding and simultaneous multithreading thereaftersuch as in the Intel® Hyperthreading technology).

While register renaming is described in the context of out-of-orderexecution, it should be understood that register renaming may be used inan in-order architecture. While the illustrated embodiment of theprocessor also includes separate instruction and data cache units134/174 and a shared L2 cache unit 176, alternative embodiments may havea single internal cache for both instructions and data, such as, forexample, a Level 1 (L1) internal cache, or multiple levels of internalcache. In some embodiments, the system may include a combination of aninternal cache and an external cache that is external to the core and/orthe processor. Alternatively, all of the cache may be external to thecore and/or the processor.

FIG. 2 is a block diagram of a processor 200 that may have more than onecore, may have an integrated memory controller, and may have integratedgraphics according to embodiments of the invention. The solid linedboxes in FIG. 2 illustrate a processor 200 with a single core 202A, asystem agent 210, a set of one or more bus controller units 216, whilethe optional addition of the dashed lined boxes illustrates analternative processor 200 with multiple cores 202A-N, a set of one ormore integrated memory controller unit(s) 214 in the system agent unit210, and special purpose logic 208.

Thus, different implementations of the processor 200 may include: 1) aCPU with the special purpose logic 208 being integrated graphics and/orscientific (throughput) logic (which may include one or more cores), andthe cores 202A-N being one or more general purpose cores (e.g., generalpurpose in-order cores, general purpose out-of-order cores, acombination of the two); 2) a coprocessor with the cores 202A-N being alarge number of special purpose cores intended primarily for graphicsand/or scientific (throughput); and 3) a coprocessor with the cores202A-N being a large number of general purpose in-order cores. Thus, theprocessor 200 may be a general-purpose processor, coprocessor orspecial-purpose processor, such as, for example, a network orcommunication processor, compression engine, graphics processor, GPGPU(general purpose graphics processing unit), a high-throughput manyintegrated core (MIC) coprocessor (including 30 or more cores), embeddedprocessor, or the like. The processor may be implemented on one or morechips. The processor 200 may be a part of and/or may be implemented onone or more substrates using any of a number of process technologies,such as, for example, BiCMOS, CMOS, or NMOS.

The memory hierarchy includes one or more levels of cache within thecores, a set or one or more shared cache units 206, and external memory(not shown) coupled to the set of integrated memory controller units214. The set of shared cache units 206 may include one or more mid-levelcaches, such as level 2 (L2), level 3 (L3), level 4 (L4), or otherlevels of cache, a last level cache (LLC), and/or combinations thereof.While in one embodiment a ring based interconnect unit 212 interconnectsthe integrated graphics logic 208, the set of shared cache units 206,and the system agent unit 210/integrated memory controller unit(s) 214,alternative embodiments may use any number of well-known techniques forinterconnecting such units. In one embodiment, coherency is maintainedbetween one or more cache units 206 and cores 202-A-N.

In some embodiments, one or more of the cores 202A-N are capable ofmulti-threading. The system agent 210 includes those componentscoordinating and operating cores 202A-N. The system agent unit 210 mayinclude for example a power control unit (PCU) and a display unit. ThePCU may be or include logic and components needed for regulating thepower state of the cores 202A-N and the integrated graphics logic 208.The display unit is for driving one or more externally connecteddisplays.

The cores 202A-N may be homogenous or heterogeneous in terms ofarchitecture instruction set; that is, two or more of the cores 202A-Nmay be capable of execution the same instruction set, while others maybe capable of executing only a subset of that instruction set or adifferent instruction set.

FIGS. 3-6 are block diagrams of exemplary computer architectures. Othersystem designs and configurations known in the arts for laptops,desktops, handheld PCs, personal digital assistants, engineeringworkstations, servers, network devices, network hubs, switches, embeddedprocessors, digital signal processors (DSPs), graphics devices, videogame devices, set-top boxes, micro controllers, cell phones, portablemedia players, hand held devices, and various other electronic devices,are also suitable. In general, a huge variety of systems or electronicdevices capable of incorporating a processor and/or other executionlogic as disclosed herein are generally suitable.

Referring now to FIG. 3, shown is a block diagram of a system 300 inaccordance with one embodiment of the present invention. The system 300may include one or more processors 310, 315, which are coupled to acontroller hub 320. In one embodiment the controller hub 320 includes agraphics memory controller hub (GMCH) 390 and an Input/Output Hub (IOH)350 (which may be on separate chips); the GMCH 390 includes memory andgraphics controllers to which are coupled memory 340 and a coprocessor345; the IOH 350 is couples input/output (I/O) devices 360 to the GMCH390. Alternatively, one or both of the memory and graphics controllersare integrated within the processor (as described herein), the memory340 and the coprocessor 345 are coupled directly to the processor 310,and the controller hub 320 in a single chip with the IOH 350.

The optional nature of additional processors 315 is denoted in FIG. 3with broken lines. Each processor 310, 315 may include one or more ofthe processing cores described herein and may be some version of theprocessor 200.

The memory 340 may be, for example, dynamic random access memory (DRAM),phase change memory (PCM), or a combination of the two. For at least oneembodiment, the controller hub 320 communicates with the processor(s)310, 315 via a multi-drop bus, such as a frontside bus (FSB),point-to-point interface such as QuickPath Interconnect (QPI), orsimilar connection 395.

In one embodiment, the coprocessor 345 is a special-purpose processor,such as, for example, a high-throughput MIC processor, a network orcommunication processor, compression engine, graphics processor, GPGPU,embedded processor, or the like. In one embodiment, controller hub 320may include an integrated graphics accelerator.

There can be a variety of differences between the physical resources310, 315 in terms of a spectrum of metrics of merit includingarchitectural, microarchitectural, thermal, power consumptioncharacteristics, and the like.

In one embodiment, the processor 310 executes instructions that controldata processing operations of a general type. Embedded within theinstructions may be coprocessor instructions. The processor 310recognizes these coprocessor instructions as being of a type that shouldbe executed by the attached coprocessor 345. Accordingly, the processor310 issues these coprocessor instructions (or control signalsrepresenting coprocessor instructions) on a coprocessor bus or otherinterconnect, to coprocessor 345. Coprocessor(s) 345 accept and executethe received coprocessor instructions.

Referring now to FIG. 4, shown is a block diagram of a first morespecific exemplary system 400 in accordance with an embodiment of thepresent invention. As shown in FIG. 4, multiprocessor system 400 is apoint-to-point interconnect system, and includes a first processor 470and a second processor 480 coupled via a point-to-point interconnect450. Each of processors 470 and 480 may be some version of the processor200. In one embodiment of the invention, processors 470 and 480 arerespectively processors 310 and 315, while coprocessor 438 iscoprocessor 345. In another embodiment, processors 470 and 480 arerespectively processor 310 coprocessor 345.

Processors 470 and 480 are shown including integrated memory controller(IMC) units 472 and 482, respectively. Processor 470 also includes aspart of its bus controller units point-to-point (P-P) interfaces 476 and478; similarly, second processor 480 includes P-P interfaces 486 and488. Processors 470, 480 may exchange information via a point-to-point(P-P) interface 450 using P-P interface circuits 478, 488. As shown inFIG. 4, IMCs 472 and 482 couple the processors to respective memories,namely a memory 432 and a memory 434, which may be portions of mainmemory locally attached to the respective processors.

Processors 470, 480 may each exchange information with a chipset 490 viaindividual P-P interfaces 452, 454 using point to point interfacecircuits 476, 494, 486, 498. Chipset 490 may optionally exchangeinformation with the coprocessor 438 via a high-performance interface439. In one embodiment, the coprocessor 438 is a special-purposeprocessor, such as, for example, a high-throughput MIC processor, anetwork or communication processor, compression engine, graphicsprocessor, GPGPU, embedded processor, or the like.

A shared cache (not shown) may be included in either processor oroutside of both processors, yet connected with the processors via P-Pinterconnect, such that either or both processors' local cacheinformation may be stored in the shared cache if a processor is placedinto a low power mode.

Chipset 490 may be coupled to a first bus 416 via an interface 496. Inone embodiment, first bus 416 may be a Peripheral Component Interconnect(PCI) bus, or a bus such as a PCI Express bus or another thirdgeneration I/O interconnect bus, although the scope of the presentinvention is not so limited.

As shown in FIG. 4, various I/O devices 414 may be coupled to first bus416, along with a bus bridge 418 which couples first bus 416 to a secondbus 420. In one embodiment, one or more additional processor(s) 415,such as coprocessors, high-throughput MIC processors, GPGPU's,accelerators (such as, e.g., graphics accelerators or digital signalprocessing (DSP) units), field programmable gate arrays, or any otherprocessor, are coupled to first bus 416. In one embodiment, second bus420 may be a low pin count (LPC) bus. Various devices may be coupled toa second bus 420 including, for example, a keyboard and/or mouse 422,communication devices 427 and a storage unit 428 such as a disk drive orother mass storage device which may include instructions/code and data430, in one embodiment. Further, an audio I/O 424 may be coupled to thesecond bus 420. Note that other architectures are possible. For example,instead of the point-to-point architecture of FIG. 4, a system mayimplement a multi-drop bus or other such architecture.

Referring now to FIG. 5, shown is a block diagram of a second morespecific exemplary system 500 in accordance with an embodiment of thepresent invention Like elements in FIGS. 4 and 5 bear like referencenumerals, and certain aspects of FIG. 4 have been omitted from FIG. 5 inorder to avoid obscuring other aspects of FIG. 5.

FIG. 5 illustrates that the processors 470, 480 may include integratedmemory and I/O control logic (“CL”) 472 and 482, respectively. Thus, theCL 472, 482 include integrated memory controller units and include I/Ocontrol logic. FIG. 5 illustrates that not only are the memories 432,434 coupled to the CL 472, 482, but also that I/O devices 514 are alsocoupled to the control logic 472, 482. Legacy I/O devices 515 arecoupled to the chipset 490.

Referring now to FIG. 6, shown is a block diagram of a SoC 600 inaccordance with an embodiment of the present invention. Similar elementsin FIG. 2 bear like reference numerals. Also, dashed lined boxes areoptional features on more advanced SoCs. In FIG. 6, an interconnectunit(s) 602 is coupled to: an application processor 610 which includes aset of one or more cores 202A-N and shared cache unit(s) 206; a systemagent unit 210; a bus controller unit(s) 216; an integrated memorycontroller unit(s) 214; a set or one or more coprocessors 620 which mayinclude integrated graphics logic, an image processor, an audioprocessor, and a video processor; an static random access memory (SRAM)unit 630; a direct memory access (DMA) unit 632; and a display unit 640for coupling to one or more external displays. In one embodiment, thecoprocessor(s) 620 include a special-purpose processor, such as, forexample, a network or communication processor, compression engine,GPGPU, a high-throughput MIC processor, embedded processor, or the like.

Embodiments of the mechanisms disclosed herein may be implemented inhardware, software, firmware, or a combination of such implementationapproaches. Embodiments of the invention may be implemented as computerprograms or program code executing on programmable systems comprising atleast one processor, a storage system (including volatile andnon-volatile memory and/or storage elements), at least one input device,and at least one output device.

Program code, such as code 430 illustrated in FIG. 4, may be applied toinput instructions to perform the functions described herein andgenerate output information. The output information may be applied toone or more output devices, in known fashion. For purposes of thisapplication, a processing system includes any system that has aprocessor, such as, for example; a digital signal processor (DSP), amicrocontroller, an application specific integrated circuit (ASIC), or amicroprocessor.

The program code may be implemented in a high level procedural or objectoriented programming language to communicate with a processing system.The program code may also be implemented in assembly or machinelanguage, if desired. In fact, the mechanisms described herein are notlimited in scope to any particular programming language. In any case,the language may be a compiled or interpreted language.

One or more aspects of at least one embodiment may be implemented byrepresentative instructions stored on a machine-readable medium whichrepresents various logic within the processor, which when read by amachine causes the machine to fabricate logic to perform the techniquesdescribed herein. Such representations, known as “IP cores” may bestored on a tangible, machine readable medium and supplied to variouscustomers or manufacturing facilities to load into the fabricationmachines that actually make the logic or processor.

Such machine-readable storage media may include, without limitation,non-transitory, tangible arrangements of articles manufactured or formedby a machine or device, including storage media such as hard disks, anyother type of disk including floppy disks, optical disks, compact diskread-only memories (CD-ROMs), compact disk rewritable's (CD-RWs), andmagneto-optical disks, semiconductor devices such as read-only memories(ROMs), random access memories (RAMs) such as dynamic random accessmemories (DRAMs), static random access memories (SRAMs), erasableprogrammable read-only memories (EPROMs), flash memories, electricallyerasable programmable read-only memories (EEPROMs), phase change memory(PCM), magnetic or optical cards, or any other type of media suitablefor storing electronic instructions.

Accordingly, embodiments of the invention also include non-transitory,tangible machine-readable media containing instructions or containingdesign data, such as Hardware Description Language (HDL), which definesstructures, circuits, apparatuses, processors and/or system featuresdescribed herein. Such embodiments may also be referred to as programproducts.

In some cases, an instruction converter may be used to convert aninstruction from a source instruction set to a target instruction set.For example, the instruction converter may translate (e.g., using staticbinary translation, dynamic binary translation including dynamiccompilation), morph, emulate, or otherwise convert an instruction to oneor more other instructions to be processed by the core. The instructionconverter may be implemented in software, hardware, firmware, or acombination thereof. The instruction converter may be on processor, offprocessor, or part on and part off processor.

FIG. 7 is a block diagram contrasting the use of a software instructionconverter to convert binary instructions in a source instruction set tobinary instructions in a target instruction set according to embodimentsof the invention. In the illustrated embodiment, the instructionconverter is a software instruction converter, although alternativelythe instruction converter may be implemented in software, firmware,hardware, or various combinations thereof. FIG. 7 shows a program in ahigh level language 702 may be compiled using an x86 compiler 704 togenerate x86 binary code 706 that may be natively executed by aprocessor with at least one x86 instruction set core 716. The processorwith at least one x86 instruction set core 716 represents any processorthat can perform substantially the same functions as an Intel processorwith at least one x86 instruction set core by compatibly executing orotherwise processing (1) a substantial portion of the instruction set ofthe Intel x86 instruction set core or (2) object code versions ofapplications or other software targeted to run on an Intel processorwith at least one x86 instruction set core, in order to achievesubstantially the same result as an Intel processor with at least onex86 instruction set core. The x86 compiler 704 represents a compilerthat is operable to generate x86 binary code 706 (e.g., object code)that can, with or without additional linkage processing, be executed onthe processor with at least one x86 instruction set core 716. Similarly,FIG. 7 shows the program in the high level language 702 may be compiledusing an alternative instruction set compiler 708 to generatealternative instruction set binary code 710 that may be nativelyexecuted by a processor without at least one x86 instruction set core714 (e.g., a processor with cores that execute the MIPS instruction setof MIPS Technologies of Sunnyvale, Calif. and/or that execute the ARMinstruction set of ARM Holdings of Sunnyvale, Calif.). The instructionconverter 712 is used to convert the x86 binary code 706 into code thatmay be natively executed by the processor without an x86 instruction setcore 714. This converted code is not likely to be the same as thealternative instruction set binary code 710 because an instructionconverter capable of this is difficult to make; however, the convertedcode will accomplish the general operation and be made up ofinstructions from the alternative instruction set. Thus, the instructionconverter 712 represents software, firmware, hardware, or a combinationthereof that, through emulation, simulation or any other process, allowsa processor or other electronic device that does not have an x86instruction set processor or core to execute the x86 binary code 706.

Embodiments of the Invention for Speculation Support to EnableVectorization

Embodiments of the invention described below employ load and gatheroperations with support for masking and speculation. These embodimentsalso report the vector elements that were successfully loaded byupdating the mask register. As a result of the inventive techniquesdescribed below, loops may be vectorized which would not otherwise bevectorized. By way of example:

j=0; for(i=0;i<N ;i++){ if(A[i+j]<K) { j=A[i]; } B[i]=j; }The above code can be vectorized by inserting data dependency checks inthe vector loop and breaking vector execution when the inter-iterationdependency occurs (i.e. condition A[i+j]<K holds). Since value of j isunknown, A[i+j] is not known to be safe to access except for the currentscalar iteration. Hence, to perform the vector comparison (A[i+j]<K) avector load of A[i+j] is needed that will treat the load of all elementsexcept the first mask-enabled element as speculative. Furthermore, amask needs to be returned indicating which elements were successfullyloaded in order to allow masking of the vector comparison instruction.In one embodiment, the loop can be vectorized as follows:

(1) Set mask vector k0 to all 1

(2) Perform a speculative vector load of A[i+j] masked by k0 to vectorregister (v0) with the success mask written into k0. The firstmask-enabled element should be loaded nonspeculatively into v0 while theremaining mask-enabled elements may be loaded speculatively. Thisguarantees that at least one bit of k0 will be set after the instructionexecutes.

(3) Perform a vector comparison of v0 to K zero-masked by k0 settingeach bit in k1 if corresponding bit in k0 is set and correspondingcondition (v0<K) is met and clearing the bit in k1 otherwise.

(4) Create a partial execution mask k2 based on mask k1. This may beaccomplished, for example, using the techniques described in theco-pending application entitled “Systems, Apparatuses, And Methods ForSetting An Output Mask IN A Destination Writemask Register From A SourceWrite Mask Register Using An Input Writemask And Immediate, filed______, serial no ______, which is assigned to the assignee of thepresent application and which is incorporated herein by reference.

(5) Predicate execution of j=A[i] using a predicate generated by ANDingk2 with (v0<K). Full vector execution will be performed if thespeculative load of A[i+j] was performed to full width and if thecondition A[i+j]<K was not met. In this case, the partial execution maskk2 will be all 1.

(6) In case of partial execution, set k0 to represent the remainingunexecuted elements in the vector and repeat execution by going to step2.

(7) Perform the vector write B[i]=j

The embodiments of the invention described below provide a solution tostep #2 in the pseudo-code above. These embodiments comprise a specialclass of speculative single instruction multiple data (“SIMD”)operations that operate on the first mask-enabled elementnon-speculatively and the remaining mask-enabled elements speculatively.These operations also clear the mask register bit when a speculativeelement is not successfully operated upon. A speculative element may notbe successfully operated upon because of a fault that is either notserviceable (e.g., such as an illegal address fault for a load) or notserviced (e.g., such as a page-not-present fault that does not need tobe serviced since the load is speculative). Whether serviceable faultson speculative elements are serviced is an implementation choice; thoughin many cases, not servicing them may be better for performance.

The most significant operations requiring such speculation support arethe SIMD load and gather operations which are described further below.Other operations contemplated within the scope of the embodiments of theinvention may include any faulting operation such as integerdivide/remainder and floating point arithmetic.

In one embodiment, the following two instructions—a speculative gatherand a speculative load—are introduced:

(1) vGatherFirstNS vI {k1}, mV

(2) vLoadFirstNS vI {k1}, m32/m64

The speculative gather is described in detail below. In one embodiment,the speculative vector load is similar, the only difference being thatit performs a vector load rather than a gather operation. As isunderstood by those of skill in the art, the difference between gatherand load is simply that a load reads in sequential addresses from memorywhereas a gather operation reads in non-contiguous addresses. In thecase of the speculative vector load that straddles a cache lineboundary, if the addressed vector in memory crosses a page boundary, oneimplementation is to load the elements on the first page and clear themask bits corresponding to the elements that lie in the second page.

In one embodiment, the gather instructions are variants of the advancedvector extensions (AVX)-3 VPGATHER [DD,DQ,QD,QQ] instructions designedby the assignee of the present application. They gather data for theelements enabled by the write mask k1 until the first fault isencountered. In one embodiment, if no faults are encountered, or if afault is encountered only on the address of the first enabled element,this instruction behaves the same as the VPGATHER counterpart. In oneembodiment, if a fault is encountered on an enabled element addressother that the first enabled one, the fault is not serviced, thedestination is left unmodified, and the write mask bit is cleared forthat element and any succeeding elements. Thus, this instruction updatesboth the destination register v1 and the write mask k1. After theinstruction executes, the write mask serves to indicate which elementswere successfully gathered.

The code for one embodiment of the vGatherFirstNS instruction is asfollows:

vGatherFirstNS v I {k1}, mV intj; bool first = TRUE; bool fault = FALSE;for 0=0; j<VLEN; j++) { / / VLEN is vector length i.e. number ofelements if(k1 [j] == 1) { if (first) { load_normal(&v1[j], &mV[j]]);first = FALSE; } else if (fault == FALSE) { fault =load_speculative(&v1[j], &mV[j]]); if (fault) k1[j] = 0; } else { k1[j]= 0; } } }

In one embodiment, load_normal (datatype*D, ptr A) loads a singleelement of size “datatype” from memory location A and writes the datainto a specific element within a vector register. This function raisesand handles faults (such as TLB, page fault) in the normal fashion.

In one embodiment, load_speculative (datatype*D, ptr A) loads a singleelement of size “datatype” from memory location A and writes the datainto a specific element within a vector register if the load does notcause any fault (TLB or page fault). If the load causes a fault, thisfunction leaves the vector element untouched.

A specific example of the operation of the vGatherFirstNS instruction isillustrated in FIG. 8. In this example, vector elements are laid outleft to right and input data elements b, c, g, and m have experienced afault condition (as indicated by the bolding and underlines). Registerv1 is initially populated with values of 7 as indicated. A value of 0 inthe input mask k1 indicates that the value of output v1 should be leftunmodified and output mask k1 should be set to zero (i.e., theseelements do not participate in the vector operation). Thus, the faultcondition on input element b is ignored. The first active element isindicated by a value of 1 in the second bit position of input mask k1and there is a fault for input element c associated with this bitposition. However, because it is the first active element of input maskk1, the value of c is passed through to output v1 and a value of 1 isupdated in output mask k1. No fault conditions exist for input elementsd, e, and f. As such, values of 1 are set in the output k1 (to indicateno fault) and the values of d, e, and f are passed through to output v1.In response to the fault condition for input element g, the value ofoutput mask k1 is set to zero for this and all successive bit positionsand the output of v1 is set to the input value of v1 (7 in the example).

As illustrated in FIG. 9, one embodiment of an apparatus for providingvectorization with speculation support includes an input index register901, a mask register 902 a sequencer 903, a base address register 904,an AND gate 905, a latch 906, an adder 907, a gather finite statemachine (FSM) 908 and an output register v1. The sequencer sequencesthrough the corresponding register elements in index register 901 andmask register 902, the outputs of which are read by the AND gate 905.The latch 906 latches on the first 1 detected in the mask register 902and causes it to output 1's to the AND gate 905 for its remainingelements (thereby causing the output of the index register 901 to bepassed through the AND gate 907). The addresses stored in the indexregister 901 are output to the adder 907 which adds the base addressfrom register 904 to the addresses from the index register 901 to arriveat the memory addresses for each of the elements to be gathered. Theseaddresses are used by the gather FSM 908 to gather the elements frommemory and output the elements in output register v1 until the secondfault condition is detected for an active input (as identified by avalue of 1 in the mask register 902).

As indicated in FIG. 10, in one embodiment, the 64-bit address and the4-bit sequencer value are input to the gather FSM 908 as well as inindication of the first active element of mask register 902 and anindication of a fault condition for each of the input addresses. For allinitial input addresses associated with an active bit in the maskregister 902 and for which a fault condition is not detected, the gatherFSM sends a request to load the element identified by the address andoutputs the data to the output register v1. In addition, the gather FSM908 sends a request to load the element identified by the address andoutputs the data to the output register v1 for the first fault conditionassociated with an active element of mask register 902. All other outputelements are set to the previous value in v1 (7's in the example shownin FIG. 8). The output mask k1 is updated with is for all data elementswhich have been successfully gathered from memory including the firstactive element for which a fault condition is detected, and is updatedwith 0s for all other data elements (i.e., those associated with orfollowing a fault condition or for which the input mask is 0). In oneembodiment the updates to the output mask k1 are performed by theprocessor core.

In one embodiment, when the sequencer 902 outputs a value of 0, thegather FSM 908 is set to the starting state. As input addresses arrive,it stores the addresses into a queue (not shown) and compares theaddresses to group them into as few cachelines as possible. It thenissues the addresses into the load queue as soon as a slot is available.When the First signal is raised, one embodiment of the gather FSM sets aflag to the address input and only this input can raise a fault. Allother inputs will not raise a fault to the core and will output zero tothe output register v1.

Compared to current solutions which implement the loop with scalarinstructions, the embodiments of the invention described herein reduceinstruction count significantly and increase performance of target loopsby enabling vectorization. Compared to current solutions, theembodiments of the invention reduce the number of instructions requiredto implement speculative operations by a factor of two and improveperformance by reducing vector loop iteration latency. Compared tocurrent vector gatherd/load instructions, the embodiments of theinvention support a partial fault condition (whereas these previousimplementations required faults be resolved for all elements in thegather/load instructions). The ability of the speculative vectoroperation to return the vector fault status through the mask register isnot present in prior solutions. Current Macroscalar implementationsrequire a two instruction sequence and a fault status register whichresults in higher dynamic instruction count, higher latency and possiblygreater implementation cost/complexity than the solution describedherein. Thus, significant benefits are realized by the describedembodiments of the invention.

Exemplary Instruction Formats

Embodiments of the instruction(s) described herein may be embodied indifferent formats. Additionally, exemplary systems, architectures, andpipelines are detailed below. Embodiments of the instruction(s) may beexecuted on such systems, architectures, and pipelines, but are notlimited to those detailed.

A vector friendly instruction format is an instruction format that issuited for vector instructions (e.g., there are certain fields specificto vector operations). While embodiments are described in which bothvector and scalar operations are supported through the vector friendlyinstruction format, alternative embodiments use only vector operationsthe vector friendly instruction format.

FIGS. 11A-11B are block diagrams illustrating a generic vector friendlyinstruction format and instruction templates thereof according toembodiments of the invention. FIG. 11A is a block diagram illustrating ageneric vector friendly instruction format and class A instructiontemplates thereof according to embodiments of the invention; while FIG.11B is a block diagram illustrating the generic vector friendlyinstruction format and class B instruction templates thereof accordingto embodiments of the invention. Specifically, a generic vector friendlyinstruction format 1100 for which are defined class A and class Binstruction templates, both of which include no memory access 1105instruction templates and memory access 1120 instruction templates. Theterm generic in the context of the vector friendly instruction formatrefers to the instruction format not being tied to any specificinstruction set.

While embodiments of the invention will be described in which the vectorfriendly instruction format supports the following: a 64 byte vectoroperand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) dataelement widths (or sizes) (and thus, a 64 byte vector consists of either16 doubleword-size elements or alternatively, 8 quadword-size elements);a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit(1 byte) data element widths (or sizes); a 32 byte vector operand length(or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8bit (1 byte) data element widths (or sizes); and a 16 byte vectoroperand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit(2 byte), or 8 bit (1 byte) data element widths (or sizes); alternativeembodiments may support more, less and/or different vector operand sizes(e.g., 256 byte vector operands) with more, less, or different dataelement widths (e.g., 128 bit (16 byte) data element widths).

The class A instruction templates in FIG. 11A include: 1) within the nomemory access 1105 instruction templates there is shown a no memoryaccess, full round control type operation 1110 instruction template anda no memory access, data transform type operation 1115 instructiontemplate; and 2) within the memory access 1120 instruction templatesthere is shown a memory access, temporal 1125 instruction template and amemory access, non-temporal 1130 instruction template. The class Binstruction templates in FIG. 11B include: 1) within the no memoryaccess 1105 instruction templates there is shown a no memory access,write mask control, partial round control type operation 1112instruction template and a no memory access, write mask control, vsizetype operation 1117 instruction template; and 2) within the memoryaccess 1120 instruction templates there is shown a memory access, writemask control 1127 instruction template.

The generic vector friendly instruction format 1100 includes thefollowing fields listed below in the order illustrated in FIGS. 11A-11B.

Format field 1140—a specific value (an instruction format identifiervalue) in this field uniquely identifies the vector friendly instructionformat, and thus occurrences of instructions in the vector friendlyinstruction format in instruction streams. As such, this field isoptional in the sense that it is not needed for an instruction set thathas only the generic vector friendly instruction format.

Base operation field 1142—its content distinguishes different baseoperations.

Register index field 1144—its content, directly or through addressgeneration, specifies the locations of the source and destinationoperands, be they in registers or in memory. These include a sufficientnumber of bits to select N registers from a PxQ (e.g. 32×512, 16x128,32×1024, 64×1024) register file. While in one embodiment N may be up tothree sources and one destination register, alternative embodiments maysupport more or less sources and destination registers (e.g., maysupport up to two sources where one of these sources also acts as thedestination, may support up to three sources where one of these sourcesalso acts as the destination, may support up to two sources and onedestination).

Modifier field 1146—its content distinguishes occurrences ofinstructions in the generic vector instruction format that specifymemory access from those that do not; that is, between no memory access1105 instruction templates and memory access 1120 instruction templates.Memory access operations read and/or write to the memory hierarchy (insome cases specifying the source and/or destination addresses usingvalues in registers), while non-memory access operations do not (e.g.,the source and destinations are registers). While in one embodiment thisfield also selects between three different ways to perform memoryaddress calculations, alternative embodiments may support more, less, ordifferent ways to perform memory address calculations.

Augmentation operation field 1150—its content distinguishes which one ofa variety of different operations to be performed in addition to thebase operation. This field is context specific. In one embodiment of theinvention, this field is divided into a class field 1168, an alpha field1152, and a beta field 1154. The augmentation operation field 1150allows common groups of operations to be performed in a singleinstruction rather than 2, 3, or 4 instructions.

Scale field 1160—its content allows for the scaling of the index field'scontent for memory address generation (e.g., for address generation thatuses 2^(scale)*index+base).

Displacement Field 1162A—its content is used as part of memory addressgeneration (e.g., for address generation that uses2^(scale)*index+base+displacement).

Displacement Factor Field 1162B (note that the juxtaposition ofdisplacement field 1162A directly over displacement factor field 1162Bindicates one or the other is used)—its content is used as part ofaddress generation; it specifies a displacement factor that is to bescaled by the size of a memory access (N)—where N is the number of bytesin the memory access (e.g., for address generation that uses2^(scale)*index+base+scaled displacement). Redundant low-order bits areignored and hence, the displacement factor field's content is multipliedby the memory operands total size (N) in order to generate the finaldisplacement to be used in calculating an effective address. The valueof N is determined by the processor hardware at runtime based on thefull opcode field 1174 (described herein) and the data manipulationfield 1154C. The displacement field 1162A and the displacement factorfield 1162B are optional in the sense that they are not used for the nomemory access 1105 instruction templates and/or different embodimentsmay implement only one or none of the two.

Data element width field 1164—its content distinguishes which one of anumber of data element widths is to be used (in some embodiments for allinstructions; in other embodiments for only some of the instructions).This field is optional in the sense that it is not needed if only onedata element width is supported and/or data element widths are supportedusing some aspect of the opcodes.

Write mask field 1170—its content controls, on a per data elementposition basis, whether that data element position in the destinationvector operand reflects the result of the base operation andaugmentation operation. Class A instruction templates supportmerging-writemasking, while class B instruction templates support bothmerging- and zeroing-writemasking. When merging, vector masks allow anyset of elements in the destination to be protected from updates duringthe execution of any operation (specified by the base operation and theaugmentation operation); in other one embodiment, preserving the oldvalue of each element of the destination where the corresponding maskbit has a 0. In contrast, when zeroing vector masks allow any set ofelements in the destination to be zeroed during the execution of anyoperation (specified by the base operation and the augmentationoperation); in one embodiment, an element of the destination is set to 0when the corresponding mask bit has a 0 value. A subset of thisfunctionality is the ability to control the vector length of theoperation being performed (that is, the span of elements being modified,from the first to the last one); however, it is not necessary that theelements that are modified be consecutive. Thus, the write mask field1170 allows for partial vector operations, including loads, stores,arithmetic, logical, etc. While embodiments of the invention aredescribed in which the write mask field's 1170 content selects one of anumber of write mask registers that contains the write mask to be used(and thus the write mask field's 1170 content indirectly identifies thatmasking to be performed), alternative embodiments instead or additionalallow the mask write field's 1170 content to directly specify themasking to be performed.

Immediate field 1172—its content allows for the specification of animmediate. This field is optional in the sense that is it not present inan implementation of the generic vector friendly format that does notsupport immediate and it is not present in instructions that do not usean immediate.

Class field 1168—its content distinguishes between different classes ofinstructions. With reference to FIGS. 11A-B, the contents of this fieldselect between class A and class B instructions. In FIGS. 11A-B, roundedcorner squares are used to indicate a specific value is present in afield (e.g., class A 1168A and class B 1168B for the class field 1168respectively in FIGS. 11A-B).

Instruction Templates of Class A

In the case of the non-memory access 1105 instruction templates of classA, the alpha field 1152 is interpreted as an RS field 1152A, whosecontent distinguishes which one of the different augmentation operationtypes are to be performed (e.g., round 1152A.1 and data transform1152A.2 are respectively specified for the no memory access, round typeoperation 1110 and the no memory access, data transform type operation1115 instruction templates), while the beta field 1154 distinguisheswhich of the operations of the specified type is to be performed. In theno memory access 1105 instruction templates, the scale field 1160, thedisplacement field 1162A, and the displacement scale filed 1162B are notpresent.

No-Memory Access Instruction Templates—Full Round Control Type Operation

In the no memory access full round control type operation 1110instruction template, the beta field 1154 is interpreted as a roundcontrol field 1154A, whose content(s) provide static rounding. While inthe described embodiments of the invention the round control field 1154Aincludes a suppress all floating point exceptions (SAE) field 1156 and around operation control field 1158, alternative embodiments may supportmay encode both these concepts into the same field or only have one orthe other of these concepts/fields (e.g., may have only the roundoperation control field 1158).

SAE field 1156—its content distinguishes whether or not to disable theexception event reporting; when the SAE field's 1156 content indicatessuppression is enabled, a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler.

Round operation control field 1158—its content distinguishes which oneof a group of rounding operations to perform (e.g., Round-up,Round-down, Round-towards-zero and Round-to-nearest). Thus, the roundoperation control field 1158 allows for the changing of the roundingmode on a per instruction basis. In one embodiment of the inventionwhere a processor includes a control register for specifying roundingmodes, the round operation control field's 1150 content overrides thatregister value.

No Memory Access Instruction Templates—Data Transform Type Operation

In the no memory access data transform type operation 1115 instructiontemplate, the beta field 1154 is interpreted as a data transform field1154B, whose content distinguishes which one of a number of datatransforms is to be performed (e.g., no data transform, swizzle,broadcast).

In the case of a memory access 1120 instruction template of class A, thealpha field 1152 is interpreted as an eviction hint field 1152B, whosecontent distinguishes which one of the eviction hints is to be used (inFIG. 11A, temporal 1152B.1 and non-temporal 1152B.2 are respectivelyspecified for the memory access, temporal 1125 instruction template andthe memory access, non-temporal 1130 instruction template), while thebeta field 1154 is interpreted as a data manipulation field 1154C, whosecontent distinguishes which one of a number of data manipulationoperations (also known as primitives) is to be performed (e.g., nomanipulation; broadcast; up conversion of a source; and down conversionof a destination). The memory access 1120 instruction templates includethe scale field 1160, and optionally the displacement field 1162A or thedisplacement scale field 1162B.

Vector memory instructions perform vector loads from and vector storesto memory, with conversion support. As with regular vector instructions,vector memory instructions transfer data from/to memory in a dataelement-wise fashion, with the elements that are actually transferred isdictated by the contents of the vector mask that is selected as thewrite mask.

Memory Access Instruction Templates—Temporal

Temporal data is data likely to be reused soon enough to benefit fromcaching. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Memory Access Instruction Templates—Non-Temporal

Non-temporal data is data unlikely to be reused soon enough to benefitfrom caching in the 1st-level cache and should be given priority foreviction. This is, however, a hint, and different processors mayimplement it in different ways, including ignoring the hint entirely.

Instruction Templates of Class B

In the case of the instruction templates of class B, the alpha field1152 is interpreted as a write mask control (Z) field 1152C, whosecontent distinguishes whether the write masking controlled by the writemask field 1170 should be a merging or a zeroing.

In the case of the non-memory access 1105 instruction templates of classB, part of the beta field 1154 is interpreted as an RL field 1157A,whose content distinguishes which one of the different augmentationoperation types are to be performed (e.g., round 1157A.1 and vectorlength (VSIZE) 1157A.2 are respectively specified for the no memoryaccess, write mask control, partial round control type operation 1112instruction template and the no memory access, write mask control, VSIZEtype operation 1117 instruction template), while the rest of the betafield 1154 distinguishes which of the operations of the specified typeis to be performed. In the no memory access 1105 instruction templates,the scale field 1160, the displacement field 1162A, and the displacementscale filed 1162B are not present.

In the no memory access, write mask control, partial round control typeoperation 1110 instruction template, the rest of the beta field 1154 isinterpreted as a round operation field 1159A and exception eventreporting is disabled (a given instruction does not report any kind offloating-point exception flag and does not raise any floating pointexception handler).

Round operation control field 1159A—just as round operation controlfield 1158, its content distinguishes which one of a group of roundingoperations to perform (e.g., Round-up, Round-down, Round-towards-zeroand Round-to-nearest). Thus, the round operation control field 1159Aallows for the changing of the rounding mode on a per instruction basis.In one embodiment of the invention where a processor includes a controlregister for specifying rounding modes, the round operation controlfield's 1150 content overrides that register value.

In the no memory access, write mask control, VSIZE type operation 1117instruction template, the rest of the beta field 1154 is interpreted asa vector length field 1159B, whose content distinguishes which one of anumber of data vector lengths is to be performed on (e.g., 128, 256, or512 byte).

In the case of a memory access 1120 instruction template of class B,part of the beta field 1154 is interpreted as a broadcast field 1157B,whose content distinguishes whether or not the broadcast type datamanipulation operation is to be performed, while the rest of the betafield 1154 is interpreted the vector length field 1159B. The memoryaccess 1120 instruction templates include the scale field 1160, andoptionally the displacement field 1162A or the displacement scale field1162B.

With regard to the generic vector friendly instruction format 1100, afull opcode field 1174 is shown including the format field 1140, thebase operation field 1142, and the data element width field 1164. Whileone embodiment is shown where the full opcode field 1174 includes all ofthese fields, the full opcode field 1174 includes less than all of thesefields in embodiments that do not support all of them. The full opcodefield 1174 provides the operation code (opcode).

The augmentation operation field 1150, the data element width field1164, and the write mask field 1170 allow these features to be specifiedon a per instruction basis in the generic vector friendly instructionformat.

The combination of write mask field and data element width field createtyped instructions in that they allow the mask to be applied based ondifferent data element widths.

The various instruction templates found within class A and class B arebeneficial in different situations. In some embodiments of theinvention, different processors or different cores within a processormay support only class A, only class B, or both classes. For instance, ahigh performance general purpose out-of-order core intended forgeneral-purpose computing may support only class B, a core intendedprimarily for graphics and/or scientific (throughput) computing maysupport only class A, and a core intended for both may support both (ofcourse, a core that has some mix of templates and instructions from bothclasses but not all templates and instructions from both classes iswithin the purview of the invention). Also, a single processor mayinclude multiple cores, all of which support the same class or in whichdifferent cores support different class. For instance, in a processorwith separate graphics and general purpose cores, one of the graphicscores intended primarily for graphics and/or scientific computing maysupport only class A, while one or more of the general purpose cores maybe high performance general purpose cores with out of order executionand register renaming intended for general-purpose computing thatsupport only class B. Another processor that does not have a separategraphics core, may include one more general purpose in-order orout-of-order cores that support both class A and class B. Of course,features from one class may also be implement in the other class indifferent embodiments of the invention. Programs written in a high levellanguage would be put (e.g., just in time compiled or staticallycompiled) into an variety of different executable forms, including: 1) aform having only instructions of the class(es) supported by the targetprocessor for execution; or 2) a form having alternative routineswritten using different combinations of the instructions of all classesand having control flow code that selects the routines to execute basedon the instructions supported by the processor which is currentlyexecuting the code.

FIG. 12 is a block diagram illustrating an exemplary specific vectorfriendly instruction format according to embodiments of the invention.FIG. 12 shows a specific vector friendly instruction format 1200 that isspecific in the sense that it specifies the location, size,interpretation, and order of the fields, as well as values for some ofthose fields. The specific vector friendly instruction format 1200 maybe used to extend the x86 instruction set, and thus some of the fieldsare similar or the same as those used in the existing x86 instructionset and extension thereof (e.g., AVX). This format remains consistentwith the prefix encoding field, real opcode byte field, MOD R/M field,SIB field, displacement field, and immediate fields of the existing x86instruction set with extensions. The fields from FIG. 11 into which thefields from FIG. 12 map are illustrated.

It should be understood that, although embodiments of the invention aredescribed with reference to the specific vector friendly instructionformat 1200 in the context of the generic vector friendly instructionformat 1100 for illustrative purposes, the invention is not limited tothe specific vector friendly instruction format 1200 except whereclaimed. For example, the generic vector friendly instruction format1100 contemplates a variety of possible sizes for the various fields,while the specific vector friendly instruction format 1200 is shown ashaving fields of specific sizes. By way of specific example, while thedata element width field 1164 is illustrated as a one bit field in thespecific vector friendly instruction format 1200, the invention is notso limited (that is, the generic vector friendly instruction format 1100contemplates other sizes of the data element width field 1164).

The generic vector friendly instruction format 1100 includes thefollowing fields listed below in the order illustrated in FIG. 12A.

EVEX Prefix (Bytes 0-3) 1202—is encoded in a four-byte form.

Format Field 1140 (EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0)is the format field 1140 and it contains 0×62 (the unique value used fordistinguishing the vector friendly instruction format in one embodimentof the invention).

The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fieldsproviding specific capability.

REX field 1205 (EVEX Byte 1, bits [7-5])—consists of a EVEX.R bit field(EVEX Byte 1, bit [7]—R), EVEX.X bit field (EVEX byte 1, bit [6]—X), and1157BEX byte 1, bit[5]—B). The EVEX.R, EVEX.X, and EVEX.B bit fieldsprovide the same functionality as the corresponding VEX bit fields, andare encoded using is complement form, i.e. ZMM0 is encoded as 1111B,ZMM15 is encoded as 0000B. Other fields of the instructions encode thelower three bits of the register indexes as is known in the art (rrr,xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by addingEVEX.R, EVEX.X, and EVEX.B.

REX′ field 1110—this is the first part of the REX′ field 1110 and is theEVEX.R′ bit field (EVEX Byte 1, bit [4]—R′) that is used to encodeeither the upper 16 or lower 16 of the extended 32 register set. In oneembodiment of the invention, this bit, along with others as indicatedbelow, is stored in bit inverted format to distinguish (in thewell-known x86 32-bit mode) from the BOUND instruction, whose realopcode byte is 62, but does not accept in the MOD R/M field (describedbelow) the value of 11 in the MOD field; alternative embodiments of theinvention do not store this and the other indicated bits below in theinverted format. A value of 1 is used to encode the lower 16 registers.In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and theother RRR from other fields.

Opcode map field 1215 (EVEX byte 1, bits [3:0]—mmmm)—its content encodesan implied leading opcode byte (0F, 0F 38, or 0F 3).

Data element width field 1164 (EVEX byte 2, bit [7]—W)—is represented bythe notation EVEX.W. EVEX.W is used to define the granularity (size) ofthe datatype (either 32-bit data elements or 64-bit data elements).

EVEX.vvvv 1220 (EVEX Byte 2, bits [6:3]—vvvv)—the role of EVEX.vvvv mayinclude the following: 1) EVEX.vvvv encodes the first source registeroperand, specified in inverted (1s complement) form and is valid forinstructions with 2 or more source operands; 2) EVEX.vvvv encodes thedestination register operand, specified in 1 s complement form forcertain vector shifts; or 3) EVEX.vvvv does not encode any operand, thefield is reserved and should contain 1111b. Thus, EVEX.vvvv field 1220encodes the 4 low-order bits of the first source register specifierstored in inverted (1 s complement) form. Depending on the instruction,an extra different EVEX bit field is used to extend the specifier sizeto 32 registers.

EVEX.U 1168 Class field (EVEX byte 2, bit [2]−U)—If EVEX.U=0, itindicates class A or EVEX.U0; if EVEXU=1, it indicates class B orEVEX.U1.

Prefix encoding field 1225 (EVEX byte 2, bits [1:0]—pp)—providesadditional bits for the base operation field. In addition to providingsupport for the legacy SSE instructions in the EVEX prefix format, thisalso has the benefit of compacting the SIMD prefix (rather thanrequiring a byte to express the SIMD prefix, the EVEX prefix requiresonly 2 bits). In one embodiment, to support legacy SSE instructions thatuse a SIMD prefix (66H, F2H, F3H) in both the legacy format and in theEVEX prefix format, these legacy SIMD prefixes are encoded into the SIMDprefix encoding field; and at runtime are expanded into the legacy SIMDprefix prior to being provided to the decoder's PLA (so the PLA canexecute both the legacy and EVEX format of these legacy instructionswithout modification). Although newer instructions could use the EVEXprefix encoding field's content directly as an opcode extension, certainembodiments expand in a similar fashion for consistency but allow fordifferent meanings to be specified by these legacy SIMD prefixes. Analternative embodiment may redesign the PLA to support the 2 bit SIMDprefix encodings, and thus not require the expansion.

Alpha field 1152 (EVEX byte 3, bit [7]—EH; also known as EVEX.EH,EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also illustratedwith α)—as previously described, this field is context specific.

Beta field 1154 (EVEX byte 3, bits [6:4]—SSS, also known as EVEX.s₂₋₀,EVEX.r₂₋₀, EVEX.rr1, EVEX.LL0, EVEX.LLB; also illustrated with βββ)—aspreviously described, this field is context specific.

REX′ field 1110—this is the remainder of the REX′ field and is theEVEX.V′ bit field (EVEX Byte 3, bit [3]—V′) that may be used to encodeeither the upper 16 or lower 16 of the extended 32 register set. Thisbit is stored in bit inverted format. A value of 1 is used to encode thelower 16 registers. In other words, V′VVVV is formed by combiningEVEX.V′, EVEX.vvvv.

Write mask field 1170 (EVEX byte 3, bits [2:0]—kkk)—its contentspecifies the index of a register in the write mask registers aspreviously described. In one embodiment of the invention, the specificvalue EVEX kkk=000 has a special behavior implying no write mask is usedfor the particular instruction (this may be implemented in a variety ofways including the use of a write mask hardwired to all ones or hardwarethat bypasses the masking hardware).

Real Opcode Field 1230 (Byte 4) is also known as the opcode byte. Partof the opcode is specified in this field.

MOD R/M Field 1240 (Byte 5) includes MOD field 1242, Reg field 1244, andR/M field 1246. As previously described, the MOD field's 1242 contentdistinguishes between memory access and non-memory access operations.The role of Reg field 1244 can be summarized to two situations: encodingeither the destination register operand or a source register operand, orbe treated as an opcode extension and not used to encode any instructionoperand. The role of R/M field 1246 may include the following: encodingthe instruction operand that references a memory address, or encodingeither the destination register operand or a source register operand.

Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, thescale field's 1150 content is used for memory address generation.SIB.xxx 1254 and SIB.bbb 1256—the contents of these fields have beenpreviously referred to with regard to the register indexes Xxxx andBbbb.

Displacement field 1162A (Bytes 7-10)—when MOD field 1242 contains 10,bytes 7-10 are the displacement field 1162A, and it works the same asthe legacy 32-bit displacement (disp32) and works at byte granularity.

Displacement factor field 1162B (Byte 7)—when MOD field 1242 contains01, byte 7 is the displacement factor field 1162B. The location of thisfield is that same as that of the legacy x86 instruction set 8-bitdisplacement (disp8), which works at byte granularity. Since disp8 issign extended, it can only address between −128 and 127 bytes offsets;in terms of 64 byte cache lines, disp8 uses 8 bits that can be set toonly four really useful values −128, −64, 0, and 64; since a greaterrange is often needed, disp32 is used; however, disp32 requires 4 bytes.In contrast to disp8 and disp32, the displacement factor field 1162B isa reinterpretation of disp8; when using displacement factor field 1162B,the actual displacement is determined by the content of the displacementfactor field multiplied by the size of the memory operand access (N).This type of displacement is referred to as disp8*N. This reduces theaverage instruction length (a single byte of used for the displacementbut with a much greater range). Such compressed displacement is based onthe assumption that the effective displacement is multiple of thegranularity of the memory access, and hence, the redundant low-orderbits of the address offset do not need to be encoded. In other words,the displacement factor field 1162B substitutes the legacy x86instruction set 8-bit displacement. Thus, the displacement factor field1162B is encoded the same way as an x86 instruction set 8-bitdisplacement (so no changes in the ModRM/SIB encoding rules) with theonly exception that disp8 is overloaded to disp8*N. In other words,there are no changes in the encoding rules or encoding lengths but onlyin the interpretation of the displacement value by hardware (which needsto scale the displacement by the size of the memory operand to obtain abyte-wise address offset).

Immediate field 1172 operates as previously described.

Full Opcode Field

FIG. 12B is a block diagram illustrating the fields of the specificvector friendly instruction format 1200 that make up the full opcodefield 1174 according to one embodiment of the invention. Specifically,the full opcode field 1174 includes the format field 1140, the baseoperation field 1142, and the data element width (W) field 1164. Thebase operation field 1142 includes the prefix encoding field 1225, theopcode map field 1215, and the real opcode field 1230.

Register Index Field

FIG. 12C is a block diagram illustrating the fields of the specificvector friendly instruction format 1200 that make up the register indexfield 1144 according to one embodiment of the invention. Specifically,the register index field 1144 includes the REX field 1205, the REX′field 1210, the MODR/M.reg field 1244, the MODR/M.r/m field 1246, theVVVV field 1220, xxx field 1254, and the bbb field 1256.

Augmentation Operation Field

FIG. 12D is a block diagram illustrating the fields of the specificvector friendly instruction format 1200 that make up the augmentationoperation field 1150 according to one embodiment of the invention. Whenthe class (U) field 1168 contains 0, it signifies EVEX.U0 (class A1168A); when it contains 1, it signifies EVEX.U1 (class B 1168B). WhenU=0 and the MOD field 1242 contains 11 (signifying a no memory accessoperation), the alpha field 1152 (EVEX byte 3, bit [7]—EH) isinterpreted as the rs field 1152A. When the rs field 1152A contains a 1(round 1152A.1), the beta field 1154 (EVEX byte 3, bits [6:4]—SSS) isinterpreted as the round control field 1154A. The round control field1154A includes a one bit SAE field 1156 and a two bit round operationfield 1158. When the rs field 1152A contains a 0 (data transform1152A.2), the beta field 1154 (EVEX byte 3, bits [6:4]—SSS) isinterpreted as a three bit data transform field 1154B. When U=0 and theMOD field 1242 contains 00, 01, or 10 (signifying a memory accessoperation), the alpha field 1152 (EVEX byte 3, bit [7]—EH) isinterpreted as the eviction hint (EH) field 1152B and the beta field1154 (EVEX byte 3, bits [6:4]—SSS) is interpreted as a three bit datamanipulation field 1154C.

When U=1, the alpha field 1152 (EVEX byte 3, bit [7]—EH) is interpretedas the write mask control (Z) field 1152C. When U=1 and the MOD field1242 contains 11 (signifying a no memory access operation), part of thebeta field 1154 (EVEX byte 3, bit [4]—S₀) is interpreted as the RL field1157A; when it contains a 1 (round 1157A.1) the rest of the beta field1154 (EVEX byte 3, bit [6-5]—S₂₋₁) is interpreted as the round operationfield 1159A, while when the RL field 1157A contains a 0 (VSIZE 1157.A2)the rest of the beta field 1154 (EVEX byte 3, bit [6-5]—S₂₋₁) isinterpreted as the vector length field 1159B (EVEX byte 3, bit[6-5]—L₁₋₀). When U=1 and the MOD field 1242 contains 00, 01, or 10(signifying a memory access operation), the beta field 1154 (EVEX byte3, bits [6:4]—SSS) is interpreted as the vector length field 1159B (EVEXbyte 3, bit [6-5]—L₁₋₀) and the broadcast field 1157B (EVEX byte 3, bit[4]—B).

FIG. 13 is a block diagram of a register architecture 1300 according toone embodiment of the invention. In the embodiment illustrated, thereare 32 vector registers 1310 that are 512 bits wide; these registers arereferenced as zmm0 through zmm31. The lower order 256 bits of the lower16 zmm registers are overlaid on registers ymm0-16. The lower order 128bits of the lower 16 zmm registers (the lower order 128 bits of the ymmregisters) are overlaid on registers xmm0-15. The specific vectorfriendly instruction format 1200 operates on these overlaid registerfile as illustrated in the table below.

Adjustable Vector Length Class Operations Registers Instruction A (FIG.11A; 1110, 1115, zmm registers Templates that U = 0) 1125, 1130 (thevector do not include length is 64 byte) the vector length B (FIG. 11B;1112 zmm registers field 1159B U = 1) (the vector length is 64 byte)Instruction B (FIG. 11B; 1117, 1127 zmm, ymm, or Templates that U = 1)xmm registers do include the (the vector vector length length is 64byte, field 1159B 32 byte, or 16 byte) depending on the vector lengthfield 1159B

In other words, the vector length field 1159B selects between a maximumlength and one or more other shorter lengths, where each such shorterlength is half the length of the preceding length; and instructionstemplates without the vector length field 1159B operate on the maximumvector length. Further, in one embodiment, the class B instructiontemplates of the specific vector friendly instruction format 1200operate on packed or scalar single/double-precision floating point dataand packed or scalar integer data. Scalar operations are operationsperformed on the lowest order data element position in an zmm/ymm/xmmregister; the higher order data element positions are either left thesame as they were prior to the instruction or zeroed depending on theembodiment.

Write mask registers 1315—in the embodiment illustrated, there are 8write mask registers (k0 through k7), each 64 bits in size. In analternate embodiment, the write mask registers 1315 are 16 bits in size.As previously described, in one embodiment of the invention, the vectormask register k0 cannot be used as a write mask; when the encoding thatwould normally indicate k0 is used for a write mask, it selects ahardwired write mask of 0xFFFF, effectively disabling write masking forthat instruction.

General-purpose registers 1325—in the embodiment illustrated, there aresixteen 64-bit general-purpose registers that are used along with theexisting x86 addressing modes to address memory operands. Theseregisters are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI,RSP, and R8 through R15.

Scalar floating point stack register file (x87 stack) 1345, on which isaliased the MMX packed integer flat register file 1350—in the embodimentillustrated, the x87 stack is an eight-element stack used to performscalar floating-point operations on 32/64/80-bit floating point datausing the x87 instruction set extension; while the MMX registers areused to perform operations on 64-bit packed integer data, as well as tohold operands for some operations performed between the MMX and XMMregisters.

Alternative embodiments of the invention may use wider or narrowerregisters. Additionally, alternative embodiments of the invention mayuse more, less, or different register files and registers.

FIGS. 14A-B illustrate a block diagram of a more specific exemplaryin-order core architecture, which core would be one of several logicblocks (including other cores of the same type and/or different types)in a chip. The logic blocks communicate through a high-bandwidthinterconnect network (e.g., a ring network) with some fixed functionlogic, memory I/O interfaces, and other necessary I/O logic, dependingon the application.

FIG. 14A is a block diagram of a single processor core, along with itsconnection to the on-die interconnect network 1402 and with its localsubset of the Level 2 (L2) cache 1404, according to embodiments of theinvention. In one embodiment, an instruction decoder 1400 supports thex86 instruction set with a packed data instruction set extension. An L1cache 1406 allows low-latency accesses to cache memory into the scalarand vector units. While in one embodiment (to simplify the design), ascalar unit 1408 and a vector unit 1410 use separate register sets(respectively, scalar registers 1412 and vector registers 1414) and datatransferred between them is written to memory and then read back in froma level 1 (L1) cache 1406, alternative embodiments of the invention mayuse a different approach (e.g., use a single register set or include acommunication path that allow data to be transferred between the tworegister files without being written and read back).

The local subset of the L2 cache 1404 is part of a global L2 cache thatis divided into separate local subsets, one per processor core. Eachprocessor core has a direct access path to its own local subset of theL2 cache 1404. Data read by a processor core is stored in its L2 cachesubset 1404 and can be accessed quickly, in parallel with otherprocessor cores accessing their own local L2 cache subsets. Data writtenby a processor core is stored in its own L2 cache subset 1404 and isflushed from other subsets, if necessary. The ring network ensurescoherency for shared data. The ring network is bi-directional to allowagents such as processor cores, L2 caches and other logic blocks tocommunicate with each other within the chip. Each ring data-path is1012-bits wide per direction.

FIG. 14B is an expanded view of part of the processor core in FIG. 14Aaccording to embodiments of the invention. FIG. 14B includes an L1 datacache 1406A part of the L1 cache 1404, as well as more detail regardingthe vector unit 1410 and the vector registers 1414. Specifically, thevector unit 1410 is a 16-wide vector processing unit (VPU) (see the16-wide ALU 1428), which executes one or more of integer,single-precision float, and double-precision float instructions. The VPUsupports swizzling the register inputs with swizzle unit 1420, numericconversion with numeric convert units 1422A-B, and replication withreplication unit 1424 on the memory input. Write mask registers 1426allow predicating resulting vector writes.

We claim:
 1. A processor for providing speculation support enabling vectorization, the processor to execute one or more instructions to perform the operations of: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
 2. The processor as in claim 1 to perform the additional operations of: storing data loaded from the first active element after servicing any detected fault condition in the first output vector register.
 3. The processor as in claim 1 to perform the additional operations of: reading each bit in succession from an input mask register, each bit having a true value to indicate each active element read from the first input vector register and a false value to indicate each inactive element read from the first input vector register.
 4. The processor as in claim 3 wherein the input mask register comprises the same physical register as the output mask register.
 5. The processor as in claim 1 to perform the additional operations of: adding a base address value to each address read from the input vector register to arrive at a memory address for the gather or load operation; and storing data loaded from each memory address in the output vector register for each active element prior to the detected fault condition.
 6. A method comprising: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing data loaded from the address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
 7. The method claim 6 further comprising: storing data loaded from an address of an active element associated with a first detected fault condition in the first output vector register.
 8. The method as in claim 6 further comprising: reading each bit in succession from an input mask register, each bit having a true value to indicate each active element read from the first input vector register and a false value to indicate each inactive element read from the first input vector register.
 9. The method as in claim 8 wherein the input mask register comprises the same physical register as the output mask register.
 10. The method as in claim 6 further comprising: adding a base address value to each address read from the input vector register to arrive at a memory address for the gather or load operation; and storing data loaded from each memory address in the output vector register for each active element prior to the detected fault condition.
 11. A computer system comprising: a memory for storing program instructions and data; a processor to execute one or more of the program instructions to perform the operations of: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.
 12. The system as in claim 11 wherein the processor is to perform the additional operations of: storing data loaded from an address of an active element associated with a first detected fault condition in the first output vector register.
 13. The system as in claim 11 wherein the processor is to perform the additional operations of: reading each bit in succession from an input mask register, each bit having a true value to indicate each active element read from the first input vector register and a false value to indicate each inactive element read from the first input vector register.
 14. The system as in claim 13 wherein the input mask register comprises the same physical register as the output mask register.
 15. The system as in claim 11 wherein the processor is to perform the additional operations of: adding a base address value to each address read from the input vector register to arrive at a memory address for the gather or load operation; and storing data loaded from each memory address in the output vector register for each active element prior to the detected fault condition.
 16. The computer system as in claim 11 further comprising: a display adapter to render graphics images in response to execution of the program code by the processor.
 17. The computer system as in claim 15 further comprising: a user input interface to receive control signals from a user input device, the processor executing the program code in response to the control signals.
 18. An apparatus comprising: means for reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; means for detecting one or more fault conditions associated with one or more of the active elements; means for storing data loaded from the address associated with the active element in a first output vector register for each active element read in succession prior to a detected fault condition on an element other than the first active element; and means for setting a bit in an output mask register to indicate the detected fault condition for each active element associated with the detected fault condition and following the detected fault condition.
 19. The apparatus claim 18 further comprising: means for storing data loaded from an address of an active element associated with a first detected fault condition in the first output vector register.
 20. The apparatus as in claim 18 further comprising: means for reading each bit in succession from an input mask register, each bit having a true value to indicate each active element read from the first input vector register and a false value to indicate each inactive element read from the first input vector register.
 21. The apparatus as in claim 20 wherein the input mask register comprises the same physical register as the output mask register.
 22. The apparatus as in claim 18 further comprising: means for adding a base address value to each address read from the input vector register to arrive at a memory address for the gather or load operation; and means for storing data loaded from each memory address in the output vector register for each active element prior to the detected fault condition. 